Abstract: The monumental task of building a fault-tolerant quantum computer with several millions qubits has motivated research into ‘hardware efficient’ architectures, which allow for the implementation of error correction without exploding the number of physical components required. The dissipative cat qubit architecture is one of these approaches. Cat qubits belong to the family of bosonic codes, where quantum information is encoded in the infinite-dimensional Hilbert space of a quantum harmonic oscillator. Thanks to the encoding of the cat qubit, one of the two errors (bit-flip) is exponentially suppressed with the ‘size’ of the cat qubit, that is without any additional hardware cost, which has enabled recent experimental realisation of a cat qubit with macroscopic bit-flip times of several tens of seconds. In this talk, I will present how one can combine dissipative cat qubits in high-rate phase-flip LDPC codes to obtain a logical qubit at a moderate hardware cost. Most importantly, the families of codes we construct are local in 2D, a highly desirable feature for some hardware platforms including superconducting circuits. Furthermore, I will show how a universal set of fault-tolerant logical gates can be realised on these codes, at the cost of adding a second planar layer of ancillary cat qubits on top of the memory block. In a second part, I will review the recent experimental progress to build the basic building blocks of this architecture and discuss the current obstacles to overcome in the near future.